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Computer Organization and Architecture Short Notes for GATE CS/IT – Last Minute Revision Guide

Computer Organization and Architecture Official GATE CS/IT Syllabus

  • Machine instructions and addressing modes
  • ALU, data-path and control unit
  • Instruction pipelining, pipeline hazards
  • Memory hierarchy: cache, main memory and secondary storage
  • I/O interface (interrupt and DMA mode)

Computer Organization and Architecture simplified and structured syllabus for our easy learning

  • Basics of Computer Design
  • Machine Instruction & Measuring CPU Performance
  • ALU, Data-path & Control Unit
  • Instruction Pipelining and Pipelining Hazards
  • Memory Hierarchy Design and Cache Memory
  • IO Interface DMA Transfer and Secondary Storage

Basics of Computer Design

Von–Neumann architecture

  • It is based on the concept of the same memory holding both data and instructions.
  • In this architecture, we have common addresses and data buses for both CPU and Memory.
  • In this architecture, CPU cannot access instructions and read/write at the same interval of time.
  • It is used for personal computers and small-scale computers

Harvard architecture

  • It is based on the concept of distinct memory models for instructions and data.
  • It has two sets of address/data buses shared by CPU and memory.
  • It allows two simultaneous memory fetches.
  • It allows CPU to fetch the instruction, and it can perform both read and write operations at the same time.
  • This architecture is more expensive than Von Neumann’s architecture.
  • It is used in microcontrollers and digital signal processing (DSP) devices

Flynn’s classification

It is a way of organizing multiple processors. It was first introduced by Flynn and is the most common approach for categorizing the systems with parallel processing capabilities.

This classification has four categories of computer systems.

  • SISD – Single Instruction, Single Data stream
  • SIMD – Single Instruction, Multiple Data stream
  • MISD – Multiple Instruction, Single Data Stream
  • MIMD – Multiple Instruction, Multiple Data stream

Note:The vector and arrays belong to SIMD (Single instruction and multiple data
streams).

Memory locations and addresses

  • For accessing the information from memory(word or byte), we require unique addresses for each location.
  • It is most widely used that numbers from 0 to 2K–1 are used for representing K values.
  • 2k address space means that there are 2k address cells, and each cell is represented with k bits number.

Q. If there are 512 G locations (words) in the memory, then find the number of
bits to represent each word uniquely.

Solution:

Total number of locations (words) = 512 G

1G = 230
512 G = 512 × 230 = 29 × 230 = 239
The number of bits required to represent each word uniquely:
= log2239
= 39 bits